adder.v			sample verilog file
adder.qsf		sample ".qsf" file (output of Quartus)
adder.net		Netlist file (output of T-VPACK)
adder.blif		BLIF file needs to be run through SIS to remove "null" errors and also manually edited to remove GROUND and VCC
adderedit.blif		 	 Edited BLIF file (Product of SIS manually edited to remove GROUND and VCC lines)